1. Field of the Invention
The present invention relates to a small imaging device used, e.g., in cellular phones. Specifically, the present invention relates to a solid state imaging device that can achieve high levels of microminiaturization, low cost, and high performance, and small equipment using the solid state imaging device.
2. Description of the Related Art
In recent years, a small imaging device that can be built even in small equipment such as a cellular phone has been under development. There are some requirements for this type of imaging device: first, the size is very small; second, the cost is low. A CMOS sensor that can reduce the cost by facilitating connectivity to peripheral circuits using a general CMOS process with logic LSI has been in the mainstream. The CMOS sensor can form a one-chip structure with a logic portion. Therefore, it also can achieve microminiaturization by forming a one-chip structure with an image processing portion. FIG. 6 shows the configuration of a conventional one-chip CMOS sensor. The one-chip CMOS sensor in FIG. 6 includes the following: a sensor 507 for converting light into an electric signal; a vertical scanning circuit 506 for driving the sensor; a horizontal scanning circuit 508; a timing generator (TG) 503; a gain control amplifier (GCA) 504 for amplifying a signal output from the sensor; an analog/digital converter (ADC) 505 for converting the output signal into a digital signal; and an image processing circuit 502.
However, there is a growing demand for not only microminiaturization and low cost, but also high performance such as sensitivity. It is difficult to contain a lighting unit, e.g., a strobe in small equipment like a cellular phone. Therefore, higher sensitivity is required particularly for the small equipment. Moreover, it is expected that cellular phones will be used instead of digital still cameras, which makes high performance increasingly important as a development theme.
In view of high performance, the following problems arise in the conventional configuration. When the logic circuit and the analog circuit (the sensor) are formed in one chip, they should be fabricated in the same process despite a difference in required electrical performance. Therefore, it is difficult to satisfy the performance of both the logic circuit and the sensor. When fine processing is employed, the sensor performance becomes poor. When processing that is not fine is employed to ensure the sensor performance, the logic portion is too large to enjoy the benefits of one chip. To avoid this, a method for using a two-chip structure has been proposed. The two-chip structure is composed of an imaging chip including the sensor and an image processing chip including the imaging processing portion.
Examples of the conventional technique related to the present invention include a method in which an imaging chip is stacked on an image processing chip, thereby reducing the mounting area and the size (JP 5(1993)-268535 A).
FIG. 7 shows a conventional imaging device with a two-chip structure of an imaging chip and an image processing chip. The imaging device in FIG. 7 allows an imaging chip 601 to operate independently regardless of the type of an image processing chip 608 by mounting the following components on the imaging chip 601: a sensor 603; vertical and horizontal scanning circuits 604, 605 for driving the sensor 603; a timing generator 602 for generating a pulse needed for the scanning circuits; a gain control amplifier 606 for amplifying a signal output from the sensor 603; and an analog/digital converter 607 for converting the output signal into a digital signal.
For this configuration, the circuits that inherently can exhibit their performance by CMOS logic, such as the timing generator 602, are still present in the imaging chip. Therefore, an improvement in performance of the sensor 603 causes an increase in area of those circuits.
This problem can be solved by mounting the timing generator 602, the gain control amplifier 606, and the analog/digital converter 607 on the image processing chip 608. However, timing pulse feed lines from the image processing chip 608 to the imaging chip 601 are increased, noise is superimposed on the feed lines, and this noise is superimposed on the output of the imaging chip 601, thus degrading the performance of the imaging chip.
It has been clear that this noise is caused by a fluctuation in current supplied to the scanning circuit that mainly drives the pixel portion. When the scanning circuit is formed using CMOS logic, the current fluctuation is due to a so-called through current generated by switching of a CMOS circuit. Although the CMOS circuit generally is characterized by low current consumption, it is well known that a very large current (through current) flows at the moment of switching. This is because both nMOS and pMOS transistors are in the on state only at the moment of switching to create a short circuit in the power supply and the ground. When wiring that controls the switching is located outside the chip, noise is superimposed on the wiring itself or a pulse transmitted through the wiring is rounded, so that noise of the power supply due to the through current is increased.